1. Field of the Invention
The present invention relates to a storage device and a control device that carry out a control by using a plurality of processors.
2. Description of the Related Art
A function of an integrated circuit (IC) that controls a hard disk device has been improved year by year. On the other hand, cost needs to be the same as that of the conventional ones, and integration of the IC has inevitably been increasingly demanded.
When the integration and functional improvement of the IC are attempted, power consumption is significantly increased and heat generation becomes large. However, since it is difficult to take measures for heat radiation of an integrated circuit of a hard disk, an amount of the heat generation needs to be restricted. There is a method of achieving a demand for improving the function that improves a clock frequency of a processor. However, improvement in the clock leads to an increase in the power consumption. In order to achieve a plurality of the processors with the lower number of ICs, the restriction of the power consumption is an important factor.
As a conventional technique that relates to the present invention, there is an optical disk device having a control circuit formed on one chip (for example, refer to Patent Document 1: Jpn. Pat. Appln. Laid-Open Publication No. 2004-5914).
In the integrated circuit for disk control, the number of the ICs decreases year by year due to progress in integration. However, performance requested for a device is more and more enhanced. In addition, an integration degree of the integrated circuit is about to be restricted in view of the heat generation and the power consumption. In addition, since a gate size directly affects the cost, a gate scale needs to be restricted to be small.
In a case where a control part of the hard disk device is configured with a single processor, control of an HDC (Hard Disk Controller) (control of an interface with a host), control of an RDC (Read Channel) (parameter transfer at read and write), and control of an SVC (Servo combo driver) (indication of a drive current value of a VCM (Voice Coil Motor) and a drive current value of an SPM (Spindle Motor)) need to be carried out by one main processor.
In the recent hard disk device, a servo sample frequency has increased to around 50 kHz, and servo sample time has reduced to around 20 μsec. In order to carry out the above control and calculation within the servo sample time, performance of the clock frequency of 500 MHz or higher is required for the main processor. Although this is not an impractical speed in the 90 nm process generation, not only a technique of pipelining becomes necessary, but also increase in a chip core area and increase in the heat generation along with a rise in the clock occur. Therefore, it becomes difficult to obtain a chip in practice.